Technical Field
The present disclosure relates to a memory system including a host device and a memory device.
Related Art
In memory systems including a host device and a memory device connected thereto, data transfer within one clock cycle in a memory system configured to operate in synchronization with a clock is generally becoming increasingly difficult with a higher operation speed of the system which increases propagation delays of clocks and data to be transmitted and received between the host and the memory devices.
In general memory systems, transmission and reception of data between the devices is performed in synchronization with data strobe signals generated within the system in order to prevent data loss caused by an increase in a data delay amount (see for example, JP2004-145999A, JP2011-216079A, and JP2011-508311A).
For encrypted communication between a host and a memory devices, both encryption and decryption are performed in synchronization with a single common clock in general memory sy stems.